During the manufacture of miniaturized devices such as integrated circuits (IC's) and the like, intermediate and/or final structures are often formed whereby a material layer that is provided on a workpiece should have a predetermined surface contour. This may occur, for example, during the formation of isolation structures between semiconductor devices.
In the formation of integrated circuits, the manufacture of isolation structures between semiconductor devices for insulating purposes is crucial. In either ULSI or in VLSI, already a very small amount of leakage current can induce significant power dissipation for the entire circuit. Therefore, it is very important to form an effective isolation between semiconductor devices. In addition, with the ongoing trend towards higher density integration, effective isolation must be provided in a smaller isolation space.
Trench isolation is one of the newer approaches that has been adopted adopted and it is used primarily for isolating devices in VLSI and ULSI. Trench isolation can be considered as a replacement for conventional LOCOS isolation. As seen in FIG. 5, in the basic STI technology, a pad layer 110 is first formed on the semiconductor wafer 100. The pad layer 110 may be formed by oxidizing a bare silicon wafer in a furnace to grow the pad oxide layer 110 of about 100 to 250 angstroms thickness. The pad oxide layer 110 is most typically formed from silicon dioxide.
Next, a furnace silicon nitride layer 120 of about 1500 to 2000 angstroms thickness is deposited on the pad oxide layer. The silicon nitride layer 120 is used as a mask layer and is formed on the pad oxide layer 110. Subsequently, a masking and etching step is performed to form trenches 130, for example about 0.4 to 0.5 μm in depth, by anisotropically etching into the silicon wafer.
Next, an oxide is deposited onto the wafer. The oxide may be a CVD oxide or a high density plasma chemical vapor deposition (HDPCVD) oxide. Typically, the oxide 140 needs to be planarized using a chemical mechanical polishing (CMP) technique.
The use of silicon nitride in the formation of trenches is a common technique. Indeed, not only is silicon nitride used in the formation of trenches for STI, but also in the formation of trenches for DRAM trench capacitors.
It has been found that when performing the CMP process to planarize the oxide layer 140, a within wafer variation in the planarity of the silicon nitride layer exists. In other words, the silicon nitride layer is not uniformly planar over an entire wafer. Especially, the silicon nitride layer usually exhibits a dish-like shape. This variation in the thickness of silicon nitride layer can be caused by the method of layer deposition and/or by intermediate process steps after the silicon nitride layer has been deposited, for example, a recess etch step during the formation of deep trench capacitors. The variation in the silicon nitride level causes variation in the planarity of the STI structures, which can severly decrease the overall quality of the final semiconductor product.